1. Field of the Invention
The present invention relates to graphics processing systems and more particularly to systems for efficiently implementing pixel processing in system side processing.
2. Background and Related Art
High function graphics processing systems have traditionally relied on specialized hardware to perform complex graphic calculations and pixel processing. The special purpose hardware was structured to rapidly and efficiently perform the processing steps.
Recent increases in the processing power of general purpose workstations, particularly RISC architecture workstations, has led to their use for graphics processing without added hardware. The use of general purpose processors to perform the complex pixel processing calculations raises many performance issues.
Pixel processing procedures contain a large amount of conditional logic resulting in the generation of numerous branch instructions. The branches, in turn, exist in many flavors to meet the specific processing requirements. Procedures with numerous branch instructions inhibit instruction scheduling efficiencies because the branches interfere with instruction pipelines and the use of an instruction cache. The presence of multiple branch flavors results in a large volume of process code with only minor differences.
Inefficient instruction scheduling and large executable code libraries reduce the ability of general purpose workstations to provide complex graphics processing with performance approaching that of systems with special purpose hardware.
A system and process for implementing pixel processing operations that limits the use of branch instructions and avoids large executable code sizes is needed.
One solution to the problem of different flavors of branch code is to define a few branch functions that can be called with varying parameters. The use of parameters avoids having separate code segments for each condition. This solution has the disadvantage of requiring increased processor overhead due to the overhead associated with function calls. The net result may be little improvement over the prior art solutions.
A second solution is to introduce new complex pixel processing instructions into the general purpose system. In effect, the new instructions replace portions of the specialized graphics hardware with specialized graphics instructions. This approach has the disadvantage of creating complicated instructions that often require multiple processing cycles making them difficult to schedule for execution. The new instructions may not be easily integrated into existing compilers and tools and may prove difficult to use in practice. Minor functional changes may render the new instructions useless. Finally, adding new complex instructions violates the Reduced Instruction Set Computer (RISC) design philosophy. Finally, this approach limits instruction branching but does not address the issue of overall code size.
Another proposed approach is to minimize code volume by building snippets of assembly language code and causing the system to assemble currently relevant snippets in the data area for execution. This procedure, in effect, provides editing of instruction sequences without the overhead penalty of function call overhead. This approach does minimize the code size but suffers from several drawbacks. The use of assembly language code makes the solution very machine specific and not very portable. Snippets of code are not aware of current processor register usage and, as a consequence, cannot be optimized based on register usage. Assembling the snippets at runtime introduces overhead to the system that will impact overall performance. This solution does not address the problem of reducing instruction branches only code size minimization.
Thus, a solution is needed that results in fewer instruction branches and a smaller code base size without significantly increasing processor overhead.